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Cypress 公司的CYV15G0404DXB是四路独立通道HOTLink II收发器,可以实现点到点或点到多点通信,在高速连接如光纤,平衡和不平衡铜传输线上传输数据,串行连接信号速率从195M波特到1500M波特.总的吞吐量高达12Gbps,采用第二代的HOTLink技术,和多种标准如ESCON, DVB-ASI, SMPTE 292M, SMPTE 259M, 以及光通路和GbE (IEEE802.3z)兼容.本文介绍了CYV15G0404DXB的主要特性,方框图以及发送与接收通路方框图, CYV15G0404DXB评估板电路图和所用材料清单(BOM)。
The CYV15G0404DXB Quad Independent-Channel HOTLink II Transceiver is a point-to-point or point-to-multipoint communications building block that allows the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195–1500 MBaud per serial link. The independence of each channel provides the ability to simultaneously transport different types of data at different signaling rates across multiple channels.
This user’s guide describes the operation and interface of the CYV15G0404DXB evaluation board. The evaluation board allows users to become familiar with the functionality of the CYV15G0404DXB.
CYV15G0404DXB套件包括:
CYV15G0404DXB-EVAL (the evaluation board)
Dear Customer letter
A CD containing
—CYV15G0404DXB data sheet
—CYV15G0404DXB Evaluation Board User’s Guide
—CYV15G0404DXB application notes
—0404EN.PDA and 0404BYP.PDA files for the DG2020 parallel data generator
—BSDL model
CYV15G0404DXB主要特性:
Quad channel transceiver for 195- to 1500-MBaud serial signaling rate
—Aggregate throughput of up to 12 Gbits/second
Second-generation HOTLink technology
Compliant with multiple standards
—ESCON, DVB-ASI, SMPTE 292M, SMPTE 259M, Fibre Channel and Gigabit Ethernet (GbE) (IEEE802.3z)
—8B/10B coded data or 10 bit uncoded data
Truly independent channels
—Each channel can perform reclocker function
—Each channel can operate at a different signaling rate
—Each channel can transport a different type of data
Selectable input/output clocking options
Internal phase-locked loops (PLLs) with no external PLL components
Selectable differential PECL-compatible serial inputs per channel
—Internal DC-restoration
Redundant differential PECL-compatible serial outputs per channel
—Source matched for 50Ω transmission lines
—No external bias resistors required
—Signaling-rate controlled edge-rates
MultiFrame Receive Framer provides alignment options
—Bit and byte alignment
—Comma or Full K28.5 detect
—Single or Multi-byte Framer for byte alignment
—Low-latency option
Synchronous LVTTL parallel interface
JTAG boundary scan
Built-In Self-Test (BIST) for at-speed link testing
Compatible with
—Fiber-optic modules
—Copper cables
—Circuit board traces
Per-channel Link Quality Indicator
—Analog signal detect
—Digital signal detect
Low-power 3W @ 3.3V typical
Single 3.3V supply
256-ball thermally enhanced BGA
0.25μ BiCMOS technology
图1.CYV15G0404DXB方框图
图2.CYV15G0404DXB发送通道方框图
图3.CYV15G0404DXB接收通道方框图
图4. CYV15G0404DXB评估板外形图
CYV15G0404DXB评估板电路图
图5.CYV15G0404DXB评估板电路图(1)
图6.CYV15G0404DXB评估板电路图(2)
图7.CYV15G0404DXB评估板电路图(3)
图8.CYV15G0404DXB评估板电路图(4)
图9.CYV15G0404DXB评估板电路图(5)
图10.CYV15G0404DXB评估板电路图(6)
图11.CYV15G0404DXB评估板电路图(7)
CYV15G0404DXB评估板材料清单(BOM):
作者：赛普拉斯半导体 来源：中华电子网
